DisplayModule

Display Module 13.2 is an expansion module for HD audio and video, using GAOYUN GW1NR series FPGA chip to output display signals, and employing the LT8618S chip for signal output conditioning.

Support the following products:

Micropython Example:

import os, sys, io
import M5
from M5 import *
from module import DisplayModule
disp = DisplayModule()
disp.display.fill(0)

class DisplayModule

Constructors

class DisplayModule(port, width, height, refresh_rate, pixel_clock, scale_w, scale_h)

Initialize the Module Display

参数:

• port (tuple) – The port to which the Module Display is connected. port[0]: not used, port[1]: dac pin.

• width (int) – The width of the Module Display.

• height (int) – The height of the Module Display.

• refresh_rate (int) – The refresh rate of the Module Display.

• pixel_clock (int) – The pixel clock of the Module Display.

• scale_w (int) – The scale width of the Module Display.

• scale_h (int) – The scale height of the Module Display.

UIFLOW2:

Methods